So I’ve managed to swim a little beyond my comfort zone with firmware! We
are currently working on a Thunderbolt 2 Hardware RAID device (RAID 5),
using the Marvell 9548 hardware RAID controller.
When the Marvell 9548 is in RAID 5 mode (amongst others) it uses DDR RAM to
cache write operations to the SSD drives during parity calculations etc. As
I understand it, when a Thunderbolt device is unplugged the Thunderbolt
controller sends a PCIe re-set command. This re-set command, if sent when
the Marvell 9548 is in the middle of a write operation (e.g. unexpected
unplugging) it can cause the unwritten data in the RAM to be dropped,
loosing part of the write operation.
At the moment our system architecture does not allow the correct power
management to allow the Marvell 9548 to finish it’s write operation and
then allow the device to go into sleep mode. There are also secondary,
related issues of managing the device power during RAID 5 auto-rebuilds and
I really need some help on two, related issues we are facing:
- Specification of an enclosure management chip + Thunderbolt specific
firmware to do the related house keeping (this will likely involve the
adapting of some standard enclosure management firmware for the specific
- Creating a firmware requirements doc for the different Thunderbolt power
states for Marvell so that the Marvell 9548 can work appropriately with the
specified enclosure management chip
The most pressing thing that I really want to achieve ASAP is the choice of
microcontroller to proceed with (with a recommendation from Marvell of the
NXP Cortext-M0) and the pin match up with the rest of our schematic so that
we can proceed with the physical PCB routing. Once we have that we can
start the firmware design in earnest, but as the hardware design and
approval actually takes a fair amount of time on its own, this is proving
to be a big bottle neck for us.
If anyone can help me out, or point me towards someone who can, that would
be massively appreciated.